The present invention relates to a transistor circuit, and more particularly to a transistor signal multiplier used in a demodulator for phase-shift keyed signals.
The digital phase modulation employing a phase-shift keying (referred to as "PSK") technique is known as one of the modulation methods in transmitting digital signals by means of carrier waves and is featured in that the phase of the carrier wave is shifted in accordance with the data of digital signals For example, the phase of the carrier wave is shifted by 0.degree., 90.degree., 180.degree., or 270.degree. for every 2 bits of the digital signal to be transmitted. It is superior in its frequency band characteristics and code error rate characteristics to other modulation methods such as the amplitude modulation, the frequency modulation and the pulse modulation, and therefore is widely used in PCM microwave communications, satellite communications, data transmission modems and the like. The PSK technique is classified into two-, four- and eight-phase ones which can transmit 1-, 2- and 3-bit data per one sampling period, respectively. The four-phase PSK, i.e., quadraphase-shift keying (QPSK), is most widely used at present.
In the QPSK technique, the digital signal to be transmitted is divided for every two bits which can take either one of the four combinations (0, 0), (0, 1), (1, 0), and (1, 1). For these four combinations, the phase of the carrier wave is shifted by 0, .pi./2, .pi., and 3/2 .pi., respectively. The 2-bit digital data of each combination is contained in the inphase component or the quadraphase component of the carrier wave.
For demodulation, a reference signal having the same phase as the carrier wave is generated. The phase of the received carrier wave is compared with the phase of the reference signal to obtain a signal P and also compared with the .pi./2-shifted phase of the reference signal to produce a signal Q. The polarities of the signals P and Q are detected to determine the combination of 2-bit data.
Thus, the demodulator requires a circuit for generating the reference signal having the same phase as the carrier wave, i.e., a reference carrier recovering circuit. For this purpose, the so-called "Costas loop method" is utilized, in which all of two synchronous-detected signals P and Q, their summed signal (P+Q), and their subtracted signal (P-Q) are multiplied by a signal multiplier, the multiplied result being supplied through a low-pass filter (LPF) to a voltage controlled oscillator (VCO). The output of the VCO is used as the reference signal.
Since the signal multiplier can be constructed of conventional double-balanced differential circuits, the carrier recovering circuit by the Costas loop method is suitable for being formed as a semiconductor integrated circuit device.
However, the multiplier according to the prior art requires a large number of circuit elements in order to perform the multiplication of four signals, because it is composed of three double-balanced differential circuits provided in parallel, two level shift circuits each coupling the adjacent two differential circuits, and a peripheral circuit for preparing the signals (P+Q) and (P-Q). As a result, the semiconductor chip on which the multiplier is formed becomes large in size. Further, the multiplied result of the four signals is derived after being passed through three stages of the double-balanced differential circuits which cause time delays by a time constant composed of a load resistor and its stray capacitance, thereby resulting in a considerable low multiplying speed. The time delays also result in an error in phase of the reference carrier. Moreover, power consumption is increased because of two level shift circuits between the double-balanced differential circuits through which a relatively large current flows.